A method illustrated in this is to design carry look ahead adders using SCMOS technology, also analyzed the effect of various parameters on the characteristics of adders, using 50 nm, spice model for SCMOS technology. The design was implemented for 16 bit and then extended for multibit bit also. Here parameters are computed and response curves are computed between all characteristics, DC and transient characteristics. The design and simulations are carried out to achieve these values approximately. Design will be carried out in Electric CAD and LTSPICE. Simulation results are verified using LTSpice. The Design rule check DRC, LVS Layout vs Schematic and Network Consistency Checks, transient checks are performed in the presented design of multibit adders. In comparison with the existing full adder designs, the present implementation will offer significant improvement in terms of frequency and noise as verified by FFT analysis for the same.

Author Name: Farhan Siddiqui, Ayoush Johari

URL: View PDF

Keywords: Full adder, SCMOS Circuit, 0.3 um C5 Process,Carry look ahead adder circuits, Transient analysis, FFT Analysis.

ISSN: 2394-9007

EISSN: 0000-0000

EOI/DOI: Volume-V, Number-III, June 201

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